In the process of manufacturing a semiconductor integrated circuit (hereinafter called “LSI”), circuit elements are three-dimensionally formed on a substrate placed in a wafer state to fabricate a desired integrated circuit. In the semiconductor integrated circuit manufacturing process, a deposition process step for generating a film formed of a desired material, a lithography process step for effecting exposure/transfer of each circuit pattern on a polymer film (hereinafter called “resist”) having reactivity to an exposure light beam, an etching process step for etch-processing a material film with the resist as a blocking film, a process step for implanting impurities, etc. are repeated a required number of times to thereby manufacture a desired integrated circuit.
A semiconductor device employed in the such process steps is provided with a detection mechanism which detects the presence or absence of the substrate and its orientation. For example, an optical transmission type wafer detection mechanism is equipped with a light emitting section and a light receiving or detecting section which detects light emitted from the light emitting section. The wafer detection mechanism detects the light outputted from the light emitting section through the light detecting section and determines the presence or absence of a wafer according to the intensity of light detected by the light detecting section. Since the light outputted from the light emitting section is directly detected by the light detecting section where the wafer is not placed on an optical path between the light emitting section and the light detecting section, for example, the value detected at the light detecting section is large and the wafer is hence judged not to exist. On the other hand, since the light that propagates from the light emitting section to the light detecting section is blocked by the wafer where the wafer is placed on the optical path between the light emitting section and the light detecting section, the value detected at the light detecting section is small and the wafer is hence judged to exist. In order to accurately detect the presence or absence of the wafer and its orientation by such an optical transmission type wafer detection mechanism, there is a need to increase the difference between the amounts of light transmitted through the wafer where the wafer is placed on the optical path between the light emitting section and the light detecting section and not placed thereon. It is thus desirable that when the wafer is placed on the optical path between the light emitting section and the light detecting section, the wafer perfectly blocks the light, or the amount of light transmitted through the wafer is reduced by reflecting, absorbing or scattering the light.
Upon the exposure in the lithography process step, an original plate in which each pattern is formed, using a material such as chromium, on a glass substrate having a cutoff property relative to the exposure light beam, is used as a mask. The mask's pattern is imaged onto a resist film on the wafer by an exposure device constituted of a scale-down projection optical system or the like to allow the resist to react. In the LSI manufacturing process of three-dimensionally forming the circuit elements, it is indispensable to align the position of each pattern on the mask with its corresponding circuit element already processed on the wafer in the previous process step. Overlay or registration marks formed on both the mask and the wafer are used upon the alignment. In the lithography process step, the amount of relative positional displacement between each formed resist pattern and the LSI element pattern already processed and formed in the previous process step is measured and the accuracy of superimposition or registration is confirmed, whereby process shipment is judged. A mark used at this time is an overlay or superimposition accuracy measurement mark (hereinafter called “registration measurement mark”). The registration mark and the superimposition mark are collectively called “alignment mark”)
A wafer alignment method using reflection marks each composed of a multilayer reflection layer in respective scribe line areas in a wafer having a plurality of exposure regions surrounded by the scribe line areas has been described in Japanese Patent Laid-Open No. Hei 5(1993)-198471. Each of the reflection marks comprises a multilayer film reflection layer whose diameter is 0.1 mm and is equivalent to one wherein a molybdenum thin film having a thickness of 3.1 nm, and a silicon thin film having a thickness of 3.6 nm are respectively alternately laminated on one another by 20 layers and the top layer is covered with a molybdenum film of 3.1 nm. Allowing the reflection mark to reflect a soft X-ray whose incident angle is 0° and whose wavelength is 13 nm, with good efficiency enables high-precision positioning of the wafer.
Japanese Patent Laid-Open No. Hei 7(1995)-283383 describes an silicon-on-sapphire (SOS) wafer in which a polysilicon layer is formed on the back surface of the SOS wafer so as to reach a thickness enough to detect an opaque object by a photosensor, and dopant such as phosphorus is implanted in the polysilicon layer to allow the SOS wafer to have conductivity. Since the SOS wafer has the polysilicon layer having optical and electrical characteristics of silicon, the presence or absence of the wafer can be detected using an optical sensor and an electric sensor of a silicon wafer processing apparatus.
A phase shift mask which has enhanced reflectance of a second layer drawing alignment pattern, has been described in Japanese Patent Laid-Open No. 2000-98583. The phase shift mask is provided with a synthetic quartz substrate, and a light-shielding layer comprising a chromium layer and a low-reflection chromium layer sequentially formed on the surface of the synthetic quartz substrate. The chromium layer is grown on only the low-reflection chromium layer in the vicinity of the second layer drawing alignment pattern to bring the neighborhood of the second layer drawing alignment pattern into optical reflectivity, thereby making it possible to observe the second layer drawing alignment pattern in high contrast.
The wavelength of light used in the wafer detection mechanism and the observation of the alignment mark should be selected as a wavelength which does not give any obstacle to the LSI manufacture. For example, such a wavelength as not to expose a resist employed in the lithography process step to light should be selected. Since the resist is exposed with light of an i line 365 nm and a g line 436 nm each corresponding to the wavelength for a general high pressure mercury lamp, or light having a wavelength not greater than them, light having a wavelength longer than these wavelengths is used as an exposure light beam. For instance, light lying in a wavelength band of from over 500 nm to under 800 nm is used.
An SOS (Silicon on Sapphire) substrate employed in the manufacture of the semiconductor integrated circuit has little light absorption and has a reflectance of 65% or less in the wavelength band ranging from over 500 nm to under 800 nm, for example. Therefore, a first problem arises in that it is difficult to detect the presence or absence of the SOS substrate by a transmission type sensor. The LSI using the SOS wafer and the SOI wafer has a second problem in that when a thin silicon layer is thermally oxidized to form an alignment mark made up of a silicon oxide film, the recognition of the alignment mark becomes difficult.
The first problem will be explained. Spectral reflectances at a wavelength band ranging from 500 nm to 800 nm are calculated using a sapphire substrate of 600 μm and an SOS substrate in which a silicon layer is formed in the sapphire substrate with 110 μm. Thus, since the reflectance of the sapphire substrate is about 10% over the entire wavelength band and there is little absorption thereat, it has an optical transmittance of 90%. The SOS substrate indicates such a spectral characteristic that the peak of a reflectance of 60% is contained in a wavelength 580 nm. Since the SOS substrate has little light absorption either and light of approximately 40% or more is transmitted through the wafer at the wafer detection mechanism, there is a problem that the wafer detection mechanism lacks the reliability of wafer detection. This problem is because the SOS substrate comprises the sapphire substrate that allows light of 500 to 800 nm to pass therethrough, and the silicon layer thin to such an extent that it allows the light of 500 to 800 nm to pass therethrough. However, an SOI (Silicon on Insulator) substrate has a fear that as the thickness of the SOI substrate becomes thin, the accuracy of detection is degraded.
The second problem will be described in detail. In the SOS substrate, an alignment mark employed in a lithography process is formed in a device isolation process. In the device isolation process, each device region that actively operates as an LSI is separated using a LOCOS (Local oxidation of silicon) method that selectively oxidizes a silicon layer in general. However, upon separating the device region by the LOCOS method, the alignment mark is formed of a silicon oxide film. Since, however, the difference in reflectance between silicon and the silicon oxide film is small, the alignment mark of the silicon oxide film cannot be observed in high contrast. Since the degree of blackout at the edge of the alignment mark depends upon the scattering of light at its edge, it depends on a step between the silicon oxide film for the alignment mark and the silicon layer for the background. Since the silicon layers for the SOI substrate and the SOS substrate are thin, a step between the silicon oxide film and silicon layer formed by thermal oxidation is small as compared with a bulk silicon wafer. Therefore, the SOI substrate and the SOI substrate are also low in the degree of blackout at the mark edge and encounter difficulties in observing the edge of the mark.
According to Japanese Patent Laid-Open No. Hei 5(1993)-198471, the reflection mark is formed of the multilayer film obtained by respectively alternately laminating the molybdenum thin film having the thickness of 3.1 nm, and the silicon thin film having the thickness of 3.6 nm on one another, and the reflectance of the reflection mark relative to the soft X-ray whose wavelength is 13 nm is improved. However, there is a need to select the refractive indices of the respective films and their thicknesses to the optimum values and form the thicknesses in the form of a multilayer film in order to solve the first and second problems. However, Japanese Patent Laid-Open No. Hei 5(1993)-198471 does not refer to a method for selecting the refractive indices of the respective films and their thicknesses. Although the reflectance of the reflection mark relative to the soft X-ray having the wavelength of 13 nm has been described in the above publication, reflectance relative to light lying in each of wavelength bands other than it has not been described therein.
In the SOS wafer described in Japanese Patent Laid-Open No. Hei 7(1995)-283383, the polysilicon layer having conductivity and opacity is provided in the back surface of the SOS wafer to thereby improve reflectance at its back surface. However, the alignment mark cannot be formed on the silicon layer using the polysilicon layer.
In the phase shift mask described in Japanese Patent Laid-Open No. 2000-98583, the chromium layer high in reflectance is deposited in the vicinity of the second layer drawing alignment pattern to thereby enhance the reflectance. When, however, the phase shift mask is applied to the manufacture of the semiconductor device, the process step for evaporating the chromium layer is added, thereby causing the fear of increases in man-hour and cost.
Although the manufacture of either the alignment mark or the constitution for improving the reflectance of the semiconductor substrate has been described in the three documents referred to above, a method for manufacturing both with good efficiency is not described therein.